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SI9142
Vishay Siliconix
SI9142
Synchronous Buck Controller for High Performance Processors
FEATURES
* * * * * Over-Voltage Protection Programmable Over-Current Protection Voltage Mode Control Precision 1.3-V, 1.6% Reference Drives N-Channel Switch and Rectifier * * * * * 800-A Quiescent Current (fs = 200 kHz) 150-A Standby Current Integrated "Power Good" Output Synchronization Under-Voltage Lockout
DESCRIPTION
The voltage mode, synchronous buck controller is designed for point-of-use dc/dc conversion in high performance server and desktop computers. High efficiency is accomplished at full load by driving high- and low-side n-channel MOSFETs. The input voltage range has been designed for 4.75 V to 13.2 V to allow use of either 5 V or 12 V. The 1-MHz switching frequency combined with the 10-MHz error amplifier provides ultra-fast transient response necessary in a high performance microprocessor power supply. SI9142 is available in a 20-pin SOIC wide-body package and specified to operate over the commercial (0 to 70C) temperature range. A demo board, SI9142DB, is available.
FUNCTIONAL BLOCK DIAGRAM
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SI9142
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to AGND VSYNC_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 7 V VSYNC_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 7 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 15 V Voltages Referenced to PGND VBST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 20 V VPGND to VAGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 V VL Short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous VREF(OUT) Short to GND. . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Continuous Power Dissipation (TA = 25C)a 20-Pin SOIC Wide-Bodyb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.45 W Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . 0 to 70C Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . -65 to 125C Lead Temperature (soldering, 10 sec) . . . . . . . . . . . . . . . . . . . . 300C TJMAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 11.6 mW/C above 25C.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.75 V to 13.2 V ROSC . . . . . . . . . . . . . . . . . . . . . . 100 k (100 kHz) to 10 k (1 MHz) VL(out), (in) Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 F VL(out) Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 mA VREF Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 F VREF Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 mA Analog and Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VL
SPECIFICATIONS
Limits Test Conditions Unless Otherwise Specifed Parameter Reference
Output Voltage Regulation Line Rejection IREF = 0 IREF = 0 to 1 mA At 10 kHz 1.30 -1.6% -10 80 1.30 1.30 +1.6% 10 V mV dB VCC = 4.75 V to 13.2 V TA = 0 to 70C
Mina
Typb
Maxa
Unit
Oscillator
Operating Frequency PWM Maximum Duty Cycle SYNC High SYNC Low Sync = Open fOSC = 200 kHz fOSC = 400 kHz IOH = -100 A IOL = 500 A 100 94 88 0.7 VL 0.3 VL 1000 kHz %
V
Output Drivers
Source/Sink I (Peak) BST - LX = 4.5 V VCC = 4.75 V H Driver L Driver 500 500 1000 1000 mA
Supply
Quiescent Current PWM Standby Current Shutdown fosc = 200 kHz VCC < 3.5 V 800 150 1200 225 A
VL
Output Voltage Line Rejection IVL = 0, VCC = 5.7 to 13.2 V IVL = 0, VCC = 4.7 to 5.7 V At 10 kHz 4.95 5.7 VIN - 0.2 V 30 6.05 V dB
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SI9142
Vishay Siliconix
SPECIFICATIONS
Limits Test Conditions Unless Otherwise Specifed Parameter SS/Enable
Source Current Fault Sink Current Logic Low Logic High 2.4 -2.5 20 -5 35 0.8 -7.5 A mA V VCC = 4.75 V to 13.2 V TA = 0 to 70C
Mina
Typb
Maxa
Unit
UVLO
Lockout Voltage Hysteresis VL Falling 3.6 200 3.8 V mV
Error Amplifier
Unity-Gain BW Product Input Bias Current Offset Voltage Output Current VCC = 5 V VNI = VREF , VFB = 1.0 V VNI = VREF Source (VFB = 0.8 V, NI = VREF) Sink (VFB = 2.4 V, NI = VREF) 0.8 -1 -15.0 10 0 0 1 15.0 -1 MHz A mV mA
PWR_GOOD
VPWR_GOOD High VPWR_GOOD Low Output Sink Current Typical Hysteresis = 1% VNI = VREF VDS 1 V VNI + 7% VNI - 17% 2 VNI +12% VNI -12% VNI + 17% VNI - 7% V mA
OVP
Threshold Voltage VNI = VREF BST - LX = 4.5 V 4.75 VICS 13.2 V VNI + 12% VNI + 17% VNI + 22% V
OCP
ICS Sink Current Notes a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. 126 170 204 A
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SI9142
Vishay Siliconix
TYPICAL CHARACTERISTICS (25C UNLESS OTHERWISE NOTED)
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SI9142
Vishay Siliconix
TYPICAL CHARACTERISTICS (25C UNLESS OTHERWISE NOTED)
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SI9142
Vishay Siliconix
PIN CONFIGURATION ORDERING INFORMATION
Part Number
SI9142CW
Temperature Range
0 to 70C
Packaging
Bulk
Ev Kit
SI9142 DB
Temperature Range
0 to 70C
Board Type
Surface Mount
PIN DESCRIPTION
Pin Number
1 2 3 4 5 6 7 8 9 10 11 12, 13 14 15 16 17 18 19 20
Symbol
NI SS/Enable FB COMP VCC VREF AGND ROSC NC SYNC PWR_GOOD PGND DL VL(out) VL(in) LX DH BST ICS Error amplifier non-inverting input
Description
Soft-Start: Capacitor programmable or logic level controlled shutdown Feedback Compensation node for the external feedback circuit Input Voltage: 4.75 V to 13.2 V 1.30 V precision reference Ground: Connect to quiet ground. External resistor to determine switching frequency Not internally connected Synchronizing Clock Power_Good window comparator output Power Ground Low-side gate driver for the synchronous rectifier 5.5-V reference for gate drive supply Reference input, connect to RC filter from VL(out) Inductor connection node High-side gate driver for the power switch Boost capacitor connection node to generate high-side gate drive Programmable over current limit
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SI9142
Vishay Siliconix
TIMING DIAGRAMS
FIGURE 1. Start-up Timing Sequence
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SI9142
Vishay Siliconix
FIGURE 2. OVP Timing Diagram
FIGURE 3. OCP Timing Diagram
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SI9142
Vishay Siliconix
DESCRIPTION OF OPERATION
The SI9142 is a voltage mode synchronous buck controller designed to power a high performance microprocessor power supply. The voltage mode control provides efficiency and cost saving advantages over current mode control in high output current converters by eliminating the current sense resistor. The SI9142 provides ultra-fast (5-sec) transient response time and all the necessary protection circuits demanded by microprocessor supply designers. Pin 1. NI - Non-Inverting Input NI is the non-inverting input of the error amplifier. For converter output voltages equal to or greater than 1.3 V, the NI pin can be connected directly to VREF. For converter output voltages less than 1.3 V, the NI pin can be connected to VREF through a voltage divider. Pin 2. SS/Enable - Soft-Start/Enable Soft-start is accomplished by connecting a capacitor from this pin to AGND. The soft-start functions as a constant current source into this capacitor. A logic low (0.8 V) on this pin disables the output gate drives; the oscillator continues to function. A logic high (2.4 V) enables the output gate drives, assuming the input voltage is above the UVLO threshold, and that no over-voltage or over-current condition exists. Pins 3 and 4. FB and COMP - Error Amplifier FB is the inverting input of the error amplifier. The voltage on this pin is also connected internally to the input terminals of the OVP and PWR_GOOD comparators for fault detection and protection. The error amplifier has 10-MHz gainbandwidth when connected to a 20-pF load with 5-V input voltage. COMP is the output of the error amplifier. The output voltage is clamped at a maximum level to avoid long delays due to saturation during large transient conditions. The minimum COMP voltage is a diode drop below the 0% duty cycle voltage; the maximum voltage is a diode drop above the 94% duty cycle voltage. Pin 5. VCC - Input Voltage The VCC pin should be connected to the input voltage for optimum performance. The input voltage range of the SI9142 is specified to operate with either +5 VDC or +12 VDC. In order to accommodate the tolerance of the +12 V, and the possibility of using this controller in 2-cell Li+ notebook applications with a battery charger, the input voltage is rated up to +15-V absolute maximum. Pin 6. VREF - Reference Voltage The reference voltage is designed to produce 1.30 V 1.6% over the line and temperature range, to produce equally tight output regulation of the converter. The reference should be decoupled with at least 100-nF capacitance. The reference is capable of driving 1mA of external load. Pins 15 and 16. VL(out) and VL(in) - +5.5-V Linear Regulator VL(out) produces a +5.5-V output used as the gate drive voltage for both the high- and low-side external MOSFETs. The gate drive voltage for the high-side MOSFET is bootstrapped (VL(out) - VDIODE) above the input voltage. VL(out) should be bypassed with at least 4.7 F of decoupling
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Pin 7. AGND - Analog Ground AGND is the analog ground for the low power circuitry in the converter. This ground should be separated locally from PGND, and should have a separate run back to the input bypass capacitors. Pin 8. ROSC - Oscillator Timing Resistor A resistor from this pin to AGND determines the internal switching frequency of the oscillator. The internal circuitry produces 10% frequency accuracy with a 1% timing resistor. The oscillator is capable of switching at up to 1 MHz. Pin 10. SYNC - Synchronization The SYNC signal is generated from the internal oscillator. When the oscillator is ramping positive, SYNC will be logic high; when the oscillator is ramping negative, SYNC will be logic low. The SYNC pin can be used to synchronize the SI9142 to an external clock. In particular, if several SI9142s have their SYNC pins shorted together, they will all switch at the same frequency and in phase, with the frequency being set by the fastest oscillator. Pin 11. PWR_GOOD - Open Collector Power Good Signal This pin signals the status of the output voltage. The window comparator is set at 12% of the voltage at the NI pin, with a tolerance of 5%. The PWR_GOOD signal is an open drain output capable of sinking 2 mA. Pins 12 and 13. PGND - Power Ground PGND is the power ground for the high power circuitry in the converter. This ground should be separated locally from AGND, and should have a separate plane run back to the input bypass capacitors. Pins 14 and 18. DL and DH - Low- and High-Side Gate Drives DH is the high-side and DL the low-side gate drive to the external MOSFETs. Both can source and sink 2.5-A peak with 4.5-V gate drives. The timing sequence of high- and low-side gate drives is shown in Figure 1. The internal break-beforemake time interval (tBBM) of 55 nsec prevents shootthrough current in the external MOSFETs. The ringing from the gate drive output's trace inductance can produce negative voltages on DH and DL as much as 2-V negative with respect to PGND. The gate drive circuit is capable of withstanding these negative voltages without any functional defects.
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SI9142
Vishay Siliconix
capacitance, and should not be used for any other external loads. VL(in) drives the internal circuitry. It should be connected through an RC filter to VL(out). Pin 17. LX - Inductor Node The LX node is used internally to float the high-side n-channel MOSFET gate drive. During the on-time of this MOSFET, the gate to source voltage will be (VL(out) - VDIODE). The LX node is also used internally as the negative sense voltage for overcurrent protection. Pin 19. BST - Bootstrap Voltage The external high-side n-channel MOSFET gate drive voltage is derived by bootstrapping the VL(out) voltage on top of the input supply voltage. The external 100-nF capacitor connected across the BST and LX pins is charged to (VL(out) VDIODE) when the external low-side MOSFETs are on. Then, when the low-side MOSFETs are turned off, BST is internally connected to DH in order to turn on the high-side MOSFET. DL is turned on at startup to ensure initial charging of the BST capacitor. Pin 20. ICS - Programmable Over-Current Protection The over-current protection circuit senses the voltage across the external high-side n-channel MOSFET to determine the presence of an over-current condition. Current sensing occurs only during the on-time of this MOSFET. The trigger level of the over-current circuit is programmable by selecting the external resistor value connected from VCC to ICS. Once the over-current circuit has been triggered, it disables both output gate drives within 250 nsec. The circuit also discharges the soft-start capacitor as shown in the timing diagram in Figure 3. Under Voltage Lock-Out (UVLO) The internal UVLO circuit is designed to prevent a converter from starting when insufficient input voltage is present. UVLO disables the oscillator, soft-start and output drives of the SI9142 until VL(out) reaches 3.8 V; see Figure 1. The UVLO circuit has 200-mV hysteresis to prevent turn-on and -off oscillations. When the oscillator is disabled, the SI9142 is in stand-by mode, and consumes only 150 A of supply current. Start-up Timing Sequence Please refer to Figure 1 for this description. When V CC reaches 4 V, VL(out) produces at least 3.8 V, and VREF has stabilized and is regulating. The UVLO circuit enables the oscillator and the soft-start circuits. Once the soft-start voltage exceeds 1.5 V, the gate drive pulses begin, with the duty cycle of the high-side MOSFET beginning at 0% and gradually increasing until the output voltage is in regulation.
APPLICATIONS
Setting the Current Limit The current limit is set by comparing the voltage drop across the external high-side n-channel MOSFET with the voltage dropped across a sense resistor connected between VCC and ICS. The ICS pin draws a constant current, and thus the equation governing the overcurrent threshold is:
170 A * R = ILimit * RMOSFET
Once the on-state resistance of the MOSFET is known, R can be selected to set the desired current limit. One caution is in order: since the MOSFET will normally be quite warm, the resistance used in the equation should be the maximum resistance at elevated temperatures, not typical resistance at 25C. The designer should also leave adequate margin above the normal output current, both to account for tolerances and noise in the IC, as well as to permit any initial high currents while charging output capacitors. The Boost Diode The application circuit shows the use of a 1N4148 diode for the boost circuit. This provides a low-cost component for this application. However, it may be advantageous in some circuits to use a Schottky diode instead. The difference is that the Schottky has less forward drop than the regular rectifier, and this in turn means a somewhat greater gate drive voltage for the external high-side MOSFET. For MOSFETs with high gate threshold and/or low transconductance, the additional gate drive may prove very beneficial in terms of the heating of the MOSFET, and in turn the efficiency of the converter. A 1/2-A, 30-V Schottky works well in this application. Grounding The SI9142 is provided with both analog and power ground pins (AGND and PGND, respectively). Because of the high gate drive currents the SI9142 can source, it is essential that these two grounds be separated. PGND should be attached to the source of the external low-side MOSFET; AGND should be attached to the small-signal components of the circuit, such as the timing resistor and the feedback resistor. Each of these grounds should be run back independently to the input line capacitors, to avoid ground loops.
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SI9142
Vishay Siliconix
FIGURE 4. High Performance Converter
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